以下代码给出了WM8904的具体配置：
wm8904_config_t wm8904Config = { .i2cConfig = {.codecI2CInstance = BOARD_CODEC_I2C_INSTANCE, .codecI2CSourceClock = 19000000U}, .recordSource = kWM8904_RecordSourceLineInput, .recordChannelLeft = kWM8904_RecordChannelLeft2, .recordChannelRight = kWM8904_RecordChannelRight2, .playSource = kWM8904_PlaySourceDAC, .slaveAddress = WM8904_I2C_ADDRESS, .protocol = kWM8904_ProtocolI2S, .format = {.sampleRate = kWM8904_SampleRate48kHz, .bitWidth = kWM8904_BitWidth16}, .mclk_HZ = 24576000U, .master = false, }; static void I2C_Config(void) { PRINTF("Configure WM8904 codec\r\n"); /* protocol: i2s * sampleRate: 48K * bitwidth:16*/ if (CODEC_Init(codecHandle, &boardCodecConfig) != kStatus_Success) { PRINTF("WM8904_Init failed!\r\n"); } /* Initial volume kept low for hearing safety. */ CODEC_SetVolume(codecHandle, kCODEC_PlayChannelHeadphoneLeft |kCODEC_PlayChannelHeadphoneRight, 0x0020); } 2.4 DMA和中断配置在RT600上做音频数据的处理推荐用DMA，从而减少对CPU资源的消耗。DMA在RT600上推荐的用法是CM33核使用DMA0，而HiFi4使用DMA1。此外，在HiFi4中使用DMA与在CM33端是有一定区别的，这个主要体现在以下几点：
需要在XOS或XTOS中注册并启用HiFi4中断。
在HiFi4中DMA操作的SRAM地址必须是non-cacheable。
需要由使用INPUTMUX注册HiFi4中断。
这些注册的中断与HiFi4的连接关系如下表所示。表中除了提供所需的中断选择之外，还显示了各个中断的中断优先级。L1中断的优先级最低，而L3中断的优先级最高。
Interrupt Description Priority Interrupt Description Priority Interrupt Description Priority0 SYS IRQ NMI 11 Interrupt selected by DSP_INT0_SEL6 L1 22 Interrupt selected by DSP_INT0_SEL17 L2
1 SOFTWARE IRQ0 L2 12 Interrupt selected by DSP_INT0_SEL7 L1 23 Interrupt selected by DSP_INT0_SEL18 L2
2 INTERNAL RTOS TIMER0 L2 13 Interrupt selected by DSP_INT0_SEL8 L1 24 Interrupt selected by DSP_INT0_SEL19 L3
3 INTERNAL RTOS TIMER1 L3 14 Interrupt selected by DSP_INT0_SEL9 L1 25 Interrupt selected by DSP_INT0_SEL20 L3
4 PROFILING IRQ L3 15 Interrupt selected by DSP_INT0_SEL10 L1 26 Interrupt selected by DSP_INT0_SEL21 L3
5 Interrupt selected by DSP_INT0_SEL0 L1 16 Interrupt selected by DSP_INT0_SEL11 L2 27 Interrupt selected by DSP_INT0_SEL22 L3
6 Interrupt selected by DSP_INT0_SEL1 L1 17 Interrupt selected by DSP_INT0_SEL12 L2 28 Interrupt selected by DSP_INT0_SEL23 L3
7 Interrupt selected by DSP_INT0_SEL2 L1 18 Interrupt selected by DSP_INT0_SEL13 L2 29 Interrupt selected by DSP_INT0_SEL24 L3
8 Interrupt selected by DSP_INT0_SEL3 L1 19 Interrupt selected by DSP_INT0_SEL14 L2 30 Interrupt selected by DSP_INT0_SEL25 L3
9 Interrupt selected by DSP_INT0_SEL4 L1 20 Interrupt selected by DSP_INT0_SEL15 L2 31 Interrupt selected by DSP_INT0_SEL26 L3
10 Interrupt selected by DSP_INT0_SEL5 L1 21 Interrupt selected by DSP_INT0_SEL16 L2 ------ ------ ------