Infrastructure
IP: An infrastructure IP is a building block used to help assemble
systems. Infrastructure IP tends to be a generic IP that moves or transforms
data
around the system using general-purpose AXI4 interfaces and does not interpret
data.
Examples of infrastructure IP are:
° AXI Register slices (for pipelining)
° AXI FIFOs (for buffering/clock conversion)
° AXI Interconnect IP and AXI SmartConnect IP (for
connecting memory-mapped IP
together)
° AXI Direct Memory Access (DMA) engines (for memory-mapped
to stream
conversion)
° AXI Performance Monitors and Protocol Checkers
(for analysis and debug)
° AXI Verification IP (for simulation-based
verification and performance analysis)
These IP are useful for connecting IP together into a system, but are not
generally
endpoints for data.
DMA常用于存储器映射和stream数据流的转换。
比如说ddr中存储了你的有效数据需要做fft fft IP的接口时stream流 ddr的数据是存储器映射，做操作需要DMA做数据转换。
A common
approach is to build systems that combine AXI4-Stream and AXI
memory-mapped IP together. Often a DMA engine can be used to move streams in
and out
of memory.
注意AXI Data width converter 和 AXI Direct Memory Access支持的AXI接口协议。
8.AXI SmartConnect IP and AXI Interconnect IP
两者都用于一些主从设备的互联（存储器映射类型）。在一些情况下, AXI SmartConnect IP可以提供高带宽的链接以及低延迟。
The Xilinx LogiCORE IP AXI Interconnect and LogiCORE IP AXI SmartConnect cores both connect one or more AXI memory-mapped master devices to one or more memory-mapped slave devices; however, the SmartConnect is more tightly integrated into the Vivado design environment to automatically configure and adapt to connected AXI master and slave IP with minimal user intervention. The AXI Interconnect can be used in all memory-mapped designs. There are certain cases for high bandwidth application where using a SmartConnect provides better optimization. The AXI SmartConnect IP delivers the maximum system throughput at low latency by synthesizing a low area custom interconnect that is optimized for important interfaces.The AXI Interconnect core IP (axi_interconnect) connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices。
今天先到这里。
参考资料：
IHI0022D
UG1037
正点原子ZYNQ嵌入式教程