当出现上图中，红色标注的信息时，simulink模型和硬件模型创建成功，接下来进行simulink模型的设计和硬件的下载验证。
Simulink模块设计RTL代码如下所示：
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY fil_led IS
port(
datain : in std_logic_vector(7 downto 0);
dataout: out std_logic_vector(7 downto 0);
clk: in std_logic;
clk_en: in std_logic;
reset: in std_logic);
end entity;
architecture rtl of fil_led is
begin
process(clk)
begin
if clk\'event and clk=\'1\' then
if reset = \'0\' then
dataout <= (others => \'0\');
elsif clk_en = \'1\' then
dataout <= datain;