1；功能：完成RGB接口转换成LVDS接口输出！
2；下图是FITI79001H的 8位LVDS时序图
3；下图是我写出来的模块的仿真结果
4；顶层代码
1 module RGB_LVDS( 2 reset, 3 ttl_clk, 4 ttl_data_in, 5 clkpn, 6 lvds_data 7 ); 8 9 input wire reset; 10 input wire ttl_clk;//50Mhz 11 input wire [27:0] ttl_data_in;//{k,hs,vs,de,r[7:0],g[7:0],b[7:0]} 12 output [7:0] lvds_data; 13 output [1:0] clkpn; 14 15 reg [27:0] ttldata_r; 16 wire lvds_71clk; 17 wire lvds_72clk; 18 wire clk; 19 wire [7:0] lvds_datah; 20 wire [7:0] lvds_datal; 21 reg [2:0] clk_conter; 22 23 wire n_reset; 24 25 reg [1:0] lvdsclkh; 26 reg [1:0] lvdsclkl; 27 28 assign n_reset=!reset; 29 30 always @(negedge ttl_clk or negedge reset ) 31 begin 32 if(!reset) 33 ttldata_r<=28\'b0; 34 else 35 ttldata_r<=ttl_data_in; 36 37 end 38 39 40 always @(negedge lvds_71clk or negedge reset ) 41 begin 42 if(!reset) 43 clk_conter<=3\'b0; 44 else if(clk_conter>=3\'d6) 45 clk_conter<=3\'b0; 46 else 47 clk_conter<=clk_conter+3\'b1; 48 49 end 50 always @(negedge lvds_71clk or negedge reset ) 51 begin 52 if(!reset) 53 begin 54 lvdsclkh<=2\'b0; 55 lvdsclkl<=2\'b0; 56 end 57 else if(clk_conter<=3\'d1) 58 begin 59 lvdsclkh<=2\'b10; 60 lvdsclkl<=2\'b10; 61 end 62 else if(clk_conter>3\'d1 && clk_conter<5) 63 begin 64 lvdsclkh<=2\'b01; 65 lvdsclkl<=2\'b01; 66 end 67 else if(clk_conter>=3\'d5) 68 begin 69 lvdsclkh<=2\'b10; 70 lvdsclkl<=2\'b10; 71 end 72 73 end 74 75 PLL7B clk_inst( 76 .areset(n_reset), 77 .inclk0(ttl_clk), 78 .c0(lvds_71clk), 79 .c1(lvds_72clk), 80 .c2(clk), 81 .locked() 82 83 ); 84 85 P28toS7 P28TOS7_INST( 86 .rst(reset), 87 .ttlclk(clk), 88 .lvdsclk71(lvds_71clk), 89 .ttl_dataw(ttldata_r), 90 .lvds_datah(lvds_datah), 91 .lvds_datal(lvds_datal) 92 93 ); 94 95 lvds_data4 LVDS_DATA_INST( 96 .datain_h(lvds_datah), 97 .datain_l(lvds_datal), 98 .outclock(lvds_72clk), 99 .dataout(lvds_data) 100 ); 101 102 LVDSCLK_PN CLKPN_INST( 103 .aclr(), 104 .datain_h(lvdsclkh), 105 .datain_l(lvdsclkl), 106 .outclock(lvds_71clk), 107 .dataout(clkpn) 108 ); 109 110 endmodule